Verilog(R) Hardware Description Language

Why learn and use Verilog if you''re a student, beginning designer, or leading edge systems designer? The naive would ignore Verilog and "standardize" by using VHDL, the result of a decade-long committee design process. A single language for the whole world would appear to: ease the training of designers and others who use descriptions, increase tool competition to lower costs, and increase design...