Since the 1970's, microprocessor-based digital platforms have been riding Moore's law, allowing for doubling of density for the same area roughly every two years.
Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes.
Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors.
General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms.
As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems.
A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses.
Dynamic binary modification tools form a software layer between a running application and the underlying operating system, providing the powerful opportunity to inspect and potentially modify every user-level guest application instruction that executes.
Datacenter networks provide the communication substrate for large parallel computer systems that form the ecosystem for high performance computing (HPC) systems and modern Internet applications.
The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs.
This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs).
Today, computer-system optimization, at both the hardware and software levels, must consider the details of the memory system in its analysis; failing to do so yields systems that are increasingly inefficient as those systems become more complex.
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons.
This book provides a comprehensive introduction to processing-in-memory (PIM) technology, from its architectures to circuits implementations on multiple memory types and describes how it can be a viable computer architecture in the era of AI and big data.
This book describes the first comprehensive approach to the optimization of interconnect architectures in 3D systems on chips (SoCs), specially addressing the challenges and opportunities arising from heterogeneous integration.
This book serves as a single-source reference to the latest advances in Approximate Computing (AxC), a promising technique for increasing performance or reducing the cost and power consumption of a computing system.
This book focuses on neuromorphic computing principles and organization and how to build fault-tolerant scalable hardware for large and medium scale spiking neural networks with learning capabilities.
This book constitutes the refereed post-conference proceedings of 9 workshops held at the 35th International ISC High Performance 2021 Conference, in Frankfurt, Germany, in June-July 2021:Second International Workshop on the Application of Machine Learning Techniques to Computational Fluid Dynamics and Solid Mechanics Simulations and Analysis; HPC-IODC: HPC I/O in the Data Center Workshop; Compiler-assisted Correctness Checking and Performance Optimization for HPC; Machine Learning on HPC Systems;4th International Workshop on Interoperability of Supercomputing and Cloud Technologies;2nd International Workshop on Monitoring and Operational Data Analytics;16th Workshop on Virtualization in High--Performance Cloud Computing; Deep Learning on Supercomputers; 5th International Workshop on In Situ Visualization.
The greatly expanded and updated 3rd edition of this textbook offers the reader a comprehensive introduction to the concepts of logic functions and equations and their applications across computer science and engineering.
This textbook introduces basic and advanced embedded system topics through Arm Cortex M microcontrollers, covering programmable microcontroller usage starting from basic to advanced concepts using the STMicroelectronics Discovery development board.
This book constitutes the thoroughly refereed post-conference proceedings of the 24th International Workshop on Job Scheduling Strategies for Parallel Processing, JSSPP 2021, held as a virtual event in May 2021 (due to the Covid-19 pandemic).
This book constitutes the proceedings of the 16th International Conference on Parallel Computing Technologies, PaCT 2021, which was held during September 13-18, 2021.
This book provides a comprehensive coverage of hardware security concepts, derived from the unique characteristics of emerging logic and memory devices and related architectures.
This book constitutes the proceedings of the 17th International Workshop on OpenMP, IWOMP 2021, held virtually in September 2021 and hosted by the High Performance Computing research group at the University of Bristol, UK.
The two-volume set LNCS 10777 and 10778 constitutes revised selected papers from the 12th International Conference on Parallel Processing and Applied Mathematics, PPAM 2017, held in Lublin, Poland, in September 2017.
This book constitutes the refereed proceedings of the 13th International Conference on Reversible Computation, RC 2021, which was held online during July 7-8, 2021.
This book describes a new, coarse-grained reconfigurable architecture (CGRA), called Blocks, and puts it in the context of computer architectures, and in particular of other CGRAs.
This book presents state-of-the-art research results from leading electronic design automation (EDA) researchers on automated approaches for generating cyber-secure, smart hardware.
This book constitutes the refereed proceedings of the 36th International Conference on High Performance Computing, ISC High Performance 2021, held virtually in June/July 2021.
This textbook introduces basic and advanced embedded system topics through Arm Cortex M microcontrollers, covering programmable microcontroller usage starting from basic to advanced concepts using the STMicroelectronics Discovery development board.
This book constitutes the thoroughly refereed post-conference proceedings of the 32nd International Workshop on Languages and Compilers for Parallel Computing, LCPC 2019, held in Atlanta, GA, USA, in October 2019.
This book constitutes revised selected papers from the workshops held at the 26th International Conference on Parallel and Distributed Computing, Euro-Par 2020, which took place in Warsaw, Poland, in August 2020.
This textbook introduces readers to mixed-signal, embedded design and provides, in one place, much of the basic information to engage in serious mixed-signal design using Cypress' PSoC.
