Computer-aided design (CAD)

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Reuse Methodology Manual
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Verilog PLI Handbook
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Understanding Behavioral Synthesis
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Direct Engineering: Toward Intelligent Manufacturing
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Formal Semantics and Proof Techniques for Optimizing VHDL Models
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Performance Analysis of Real-Time Embedded Software
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Switching Theory for Logic Synthesis
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Reuse Techniques for VLSI Design
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Principles of Verilog PLI
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Architecture and CAD for Deep-Submicron FPGAS
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Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods
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Optimal VLSI Architectural Synthesis
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129.50 £
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Verilog(R) Hardware Description Language
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Survey of High-Level Synthesis Systems
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High-Level VLSI Synthesis
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179.50 £
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Symbolic Analysis for Automated Design of Analog Integrated Circuits
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Integrating Functional and Temporal Domains in Logic Design
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SPECC: Specification Language and Methodology
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Modeling, Verification and Exploration of Task-Level Concurrency in Real-Time Embedded Systems
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Timing Optimization Through Clock Skew Scheduling
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Function/Architecture Optimization and Co-Design of Embedded Systems
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Interconnects in VLSI Design
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Languages for Digital Embedded Systems
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Sequential Logic Testing and Verification
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High - Level Synthesis
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Synthesis Approach to Digital System Design
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129.50 £
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SECD Microprocessor
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Field-Programmable Gate Arrays
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179.50 £
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Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
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IDDQ Testing of VLSI Circuits
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Boundary-Scan Test
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Asymptotic Waveform Evaluation
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Assessing Fault Model and Test Quality
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VHDL'92
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Application-Driven Architecture Synthesis
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Algorithms for Synthesis and Testing of Asynchronous Circuits
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Wave Pipelining: Theory and CMOS Implementation
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Design Automation for Timing-Driven Layout Synthesis
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Digital BiCMOS Integrated Circuit Design
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Logic Synthesis and Optimization
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129.50 £
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Computer-Aided Verification
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Electronic CAD Frameworks
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VHDL for Simulation, Synthesis and Formal Proofs of Hardware
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179.50 £
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Cad Frameworks
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Formal Approach to Hardware Design
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Circuit Synthesis with VHDL
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Analog Device-Level Layout Automation
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